Semiconductor memory devices have been highly integrated for satisfying high performance and low manufacture costs of semiconductor memory devices which are required by users. Since integration degree of the semiconductor memory devices is an important factor in determining product price, high integrated semiconductor memory devices may be increasingly demanded. Integration degree of typical two-dimensional or planar semiconductor memory devices may be primarily determined by the area occupied by a unit memory cell, such that it may be greatly influenced by the level of a technology for forming fin patterns. However, the extremely expensive processing equipment needed to increase pattern fineness may set a practical limitation on increasing the integration degree of the two-dimensional or planar semiconductor devices.
To overcome the above limitations, three-dimensional semiconductor memory devices having three-dimensionally arranged memory cells have been proposed. However, in order to mass produce three-dimensional semiconductor memory devices, new process technologies should be developed in such a manner that can provide a lower manufacturing cost per bit than two-dimensional memory devices while maintaining or exceeding their level of reliability.